In this set of articles, I will walk through the essence of the 4321 design project, so you can survive even with zero layout experience (like I was). It will be a huge learning curve, but don’t be scared.

Think of this as a process of successive approximation (Shepard’s favorite exam technique): make an initial attempt, realize how bad it is, learn something new, refine it, and repeat.

This guide is meant to help you converge faster, dodging the early traps and misjudgments we ran into and focusing on what actually matters.

Hopefully, this means less pain and suffering, and more appreciation for the real beauty of custom layout. Enjoy!

Contents

1. Intro to 4321 Layout (this article)
2. Inverter (PS4)
   • Layout
   • DRC
   • LVS
   • Virtuoso FAQ
3. Project Plan
   • Architecture
   • ISA
   • Floorplan
4. Adder and Shifter (PS6-7)
   • Design
   • Schematic
   • Carry Circuit Walkthrough
   • 1-Bit Adder
   • 8-Bit Adder
   • Shifter
5. SRAM (PS8)
   • SRAM Array
   • Decoder
   • Read Write
   • Testing
   • What If Things Don’t Fit
6. Overall (PS9)
   • Power Grid
   • Data Path
   • PLA
   • Control Path
   • DRC and LVS Tips
   • Wrap Up!

Appendix. Pictures!
Link. Offical Course Page
Link. My Class Notes
Link. Testing Tutorial by Charlotte Chen

About

Specs:

• 1100 µm² core area
• 4 Metal layers
• 2 GHz frequency
• 2.1 µm data path bit pitch (2 SRAM columns)
• DRC and LVS clean

Configuration:

• Static CMOS ripple-carry adder
• Transmission gate logarithmic shifter (buffered)
• 4x16 physical SRAM (static decoding, 2-column MUX)
• Pseudo-NMOS ratio PLA
• Master-slave accumulator
• C²MOS bus drivers

Disclaimer

mg-04-io is a personal blog. It is not affiliated with Columbia EE or BioEE.

• This article is not an official TA guide. It is a supplement of the On-line CAD tutorials
• This guide is never intended to help you cheat. A lot of the circuits/schematics/stick diagrams/layouts are coming from our older design iterations, and will definitely fail if you copy directly

Our project is FAR from perfect. In fact, when I was writing this, I constantly cry about how much I still don’t know about Cadence Virtuoso, and how our layout can be more efficient in this and that ways.

That’s okay.

The goal of this project is to get something done, and done well, not perfectly. This is an older technology node, intended for learning and practice, so don’t pull your hair out.

Caveats

• This guide is based on our design project. As the design evolved, there are inevitably some naming inconsistencies. Nevertheless, all labels should make common sense and fit local context.
• Layout thumbnails may not render properly on some platforms. You can always view the full image in a new tab.
• There are suboptimal designs from the early (and late) stages of our project. I point out the obvious ones, but if you
  • Spot any mistakes or inefficiencies
  • Have suggestions on improving this guide
  • Want to share your layout/experience

  Feel free to contact me. I am MORE THAN HAPPY to include it!

• These articles focus primarily on layout, but testing is equally important
  • Check out the Testing Tutorial by Charlotte
• We did not explore much in Virtuoso’s design automation features. This is an area worth studying on
• TSMC, please don’t sue me! (All layouts and figures shown are sanitized academic work intended solely for peer learning purposes. No NDA violations intended)

General FAQ, Advice, and Folklore

This is a generic FAQ. You can find specific debugging tips in later articles

Logistics

What are the prereq?

Officially: ECircuits and Fundies
Realistically: a resilient spine, caffeine metabolism, and enough tears…

Find a good teammate.

Half of the class had teammate issues; the other half were the teammate issues

Should I take this class for fun?

Yes, if you enjoy circuits, symmetry, compulsive optimization, or the unique pleasure of being tortured by Shepard.

Workload

Do the PSets get harder and harder?

Check out a few extremely accurate reviews from CULPA

Yes, and not linearly.
Consider PS4 the bare minimum. You will likely need a few all-nighters after that
START EARLY!!! Start them the day they are released!!!

Do they give extensions?

Not officially, but TAs are typically nice
The real question is: will an extension actually help you?

• If you are stuck on some last-minute bugs or sicknesses: absolutely
• If you are fundamentally behind: almost certainly not.

At that point, you are not buying time. You are taking out a high-interest loan… until you declare layout-rupcy

How should my partner and I coordinate?

Introducing “Out of Order Layout”:
Most of the design projects can be parallelized: design, schematic, layout, testing, and writing the report. Just make sure you can handle the “dependencies” well

Resources

Ask Prof and TAs.

Bring questions to class, to recitations, to office hours. Let Shepard roast your masterpiece.

Ask people around you.

Your classmates know things you don’t.
They also know things you don’t know you don’t know.
Talk to them. Compare (and steal) their layouts.

Ask Chat.

LLMs are helpful, especially at fetching and reading instructions and manuals. Of course, you can’t upload any TSMC NDA material to Chat and ask it lay it out for you, but it is super useful at explaining concepts and interpreting errors.

How much should we read the textbook?

Below are the textbook chapters I found useful for the project:

• 1 Introduction
• 3.3 Layout Design Rules
• 4.3 RC Delay Model
• 9.2.5.1 CMOS with Transmission Gates
• 10.3.1 Conventional CMOS Latches
• 11.2.1 Single-Bit Addition
• 11.8.1 Funnel Shifter
• 12.2.1-3 SRAM Cells
• 12.7 Programmable Logic Arrays

What are some other resources?

There are a lot, but pretty soon, your brain will reject new PDFs.
This guide serves to distill those resources, linking the ones that I find helpful.

Design

Run DRC and LVS early and often.

Small mistakes are cheap early and exponentially expensive later. Verify in small increments and hierarchies

Don’t be messy.

Symmetry, consistency, and hierarchy will save you from debugging hell. “Messy but working” layouts will stab you some point in the futures.

Don’t chase perfect.

Don’t stress about getting anything perfect on the first pass. You will almost certainly revisit, modify, and sometimes completely nuke them as your design evolves. It’s part of the process.

Don’t blindly follow Shepard.

He’s absolutely brilliant, but he can be sometimes off by an index, an inverter, or a 90-degree rotation, whether intentional or not. So make sure you understand what’s happening yourself.

What if my layout sucks?

• Before PS7: RESTART, NOW!
• After PS8: Accept your fate, BS the project, and lock in for the exams

What are some examples that suck?

• Go to StudyDocu or similar sites. Most of what’s there is hot garbage. People upload their worst work and call it “resources” :)
• Get on LinkedIn, stalk some seniors and masters, check their “projects”. If they even bother putting their layout, chances are it probably sucks anyway.
• I’ll also share some of our own failed designs, as concrete examples of what not to do.

Grading

This class is curved, so if you are an A tier student putting in your A tier work, you should expect an A tier grade.

How will the project be graded?

Shepard will grade all projects himself, which leaves no room for BS.

This is actually a blessing compared to leaving grading to EE TAs (more often, CAs or graders) who treat it like a paycheck task, rather than any academic responsibility.

What is the distribution?

The letter grade distribution was not published in Fall 2025, but here’s the project distribution:

It’s quite a left-heavy tail, with a similar mean to exams, but a much higher variance

• This means even though the project worths half as the Final, it has the same power to boost/bomb your final grade

How are the exams?

They are relatively easy to prepare. There are two types of problems:

1. Freebies
   Straightforward. Some may be quite computational, but you’ll be fine as long as you hold your ground.
2. Problems that “tell the boys apart from the men” (according to Shepard who was “not trying to be sexist”)
   Multi-part problems that require complex calculations or new concepts/equations, things that you haven’t seen. Sometimes even the TA got them wrong. Sometimes Shepard himself found the problem unsolvable. Who knows…

Over the years, the proportion of the second type has increased, as Shepard was “running out of easy problems”

The point is: if you fail, the class fails with you. If you can’t solve the trick questions, neither can most of the class. Don’t stress too much about the exam.

I’ve thought of writing a “4321 Exam Guide,” but I don’t think obsessing over exam tricks is productive in the long run. Get a life!

• You can check out some class notes here

More to be added…

Special Thanks

Many thanks to the following for their help and guidance throughout this project:

• My teammate Charlotte Chen;
• Professor Ken Shepard;
• TAs Kaden Du, James Jagielski;
• Former students Yuxi Zhang, Yingrui Wei;
• Current students David Kim, Stephen Ogunmwonyi, Simon Mao, Nico Alarcon.

Additional thanks to William Wang on sharing his PLA layout